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Kharate, G. K.
- Ge/Si Hetero-Junction Hetero-Gate PNPN TFET with Hetero-Dielectric BOX to Improve ION/IOFF
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Authors
Affiliations
1 Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Nashik – 422105, Maharashtra, IN
2 Vishwabharti Academy’s College of Engineering, Savitribai Phule Pune University, Ahmednagar - 414201, Maharashtra, IN
1 Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Nashik – 422105, Maharashtra, IN
2 Vishwabharti Academy’s College of Engineering, Savitribai Phule Pune University, Ahmednagar - 414201, Maharashtra, IN
Source
Indian Journal of Science and Technology, Vol 10, No 14 (2017), Pagination:Abstract
Objective: PNPN TFET is a semiconductor device in which the gate controls the source to channel tunneling current through modulation of band-to-band tunneling. Silicon film thickness is also optimized to remove the kink effect. Methods/ Statistical Analysis: As the Silicon device technology as downsized to nanometers, it experiences certain issues like short channel effects, low ION/IOFF and low Sub-threshold Slope. The hetero-gate dielectric structure is designed with the addition of a hetero-dielectric Buried Oxide (BOX) on the doped substrate for reduction of ambipolar current and improvement of tunneling current at drain and source side respectively. The hetero-dielectric BOX has SiO 2 dielectric below source/channel regions and HfO2 below the drain region. Findings: The proposed device type is of Ge/Si Hetero-junction hetero-gate dielectric with hetero-dielectric BOX PNPN Tunnel FET with low bandgap material at source region increases the tunneling probability and hence improves ION. Various combinations of the simulation where executed with reference to channel, source, drain and N pocket doping for getting the optimized results for Id-Vg characteristics. The entire simulations were done in licensed Cogenda TCAD version 1.7.4 software. The hetero-gate dielectric improves the ION and suppresses the ambipolar current. Also DIBN effect gets reduced because drain current is not varied with changes in Vds(V) values with respect to Vgs(V) values. With the proposed device we obtained the performance parameters as ION=1.24mA/μm, SS=44.66mv/dec and ION/IOFF=3.47×1012. Applications/Improvements: Modeled PNPN TFET had resulted in improved performance in-terms of ION/IOFF ratio, using low band gap material and hence is best alternative over the conventional CMOS devices for the low power and moderate speed applications of FPGA.Keywords
Ambipolar Behavior, Band-to-Band Tunneling, Hetero-Dielectric BOX, Hetero-Gate, Power Delay Product (PDP), Sub-Threshold Slope, Tunnel FETFull Text
- Performance Analysis of Emerging Interconnects Driven by Devices beyond CMOS
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Authors
Affiliations
1 Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Nashik – 422105, Maharashtra, IN
2 Vishwabharti Academy’s College of Engineering, Savitribai Phule Pune University, Ahmednagar – 414201, Maharashtra, IN
1 Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Nashik – 422105, Maharashtra, IN
2 Vishwabharti Academy’s College of Engineering, Savitribai Phule Pune University, Ahmednagar – 414201, Maharashtra, IN
Source
Indian Journal of Science and Technology, Vol 10, No 27 (2017), Pagination:Abstract
Objective: This paper analyses the performances of Multi Walled Carbon Nanotube (MWCNT), Mixed CNT Bundle (MCB), and Multilayer Graphene Nanoribbon (MLGNR) interconnects incorporated with Carbon Nanotube Field-Effect Transistor (CNFET) and Tunnel Field-Effect Transistor (TFET) technologies. Methods/Statistical Analysis: The performances of the circuits are evaluated at the 32-nm node. HSPICE is used for the simulation of the driver interconnect load framework. The performance parameters, viz. power dissipation, propagation delay, and power delay product (PDP), are assessed, and it is found that a CNFET driver can reduce the propagation delay in MLGNR interconnects by 96%, 38%, and 30%, for local, intermediate, and global interconnect lengths, respectively, in comparison with the TFET driver. Findings: By using a TFET driver, the power dissipation in MLGNR is reduced by 99%, 45%, and 63%, for local, intermediate, and global levels, respectively, compared to the CNFET driver. The PDP of MLGNR is reduced by 99%, 37%, and 47% for local, intermediate, and global levels, respectively, by using a TFET driver instead of a CNFET driver. Applications/Improvements: MLGNR shows lesser propagation delay, power dissipation, and PDP than the MWCNT and MCB interconnects; hence, it is considered the best candidate to replace Cu interconnects in Very-Large-Scale Integration (VLSI) chips.Keywords
Copper, Driver Interconnect Load. Integrated Circuits, Mixed CNT Bundle, Multilevel Graphene Nano Ribbon, Multiwalled Carbon Nanotubes, Power Delay Product, Tunnel Field Effect Transistor, Very-Large-Scale-IntegrationFull Text
- Defective Ground Corner Rounded Ultra-Wideband Microstrip Patch Antenna for Bio-Medical Applications
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Authors
D. D. Ahire
1,
G. K. Kharate
1
Affiliations
1 Department of Electronics and Telecommunication Engineering, Matoshri College of Engineering and Research Centre, IN
1 Department of Electronics and Telecommunication Engineering, Matoshri College of Engineering and Research Centre, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 4 (2018), Pagination: 462-466Abstract
In this research work, design of Ultra-Wide-band microstrip line feed partial ground structure corner rounded rectangular microstrip patch antenna is presented. Design is implemented on FR4 substrate, and results implies that, just by making lower corners of rectangular patch and upper corners of partial ground rounded form sharp edges, good impedance bandwidth is achieved for the proposed antenna. Presented design full fill the essential bandwidth, needed for Ultra-Wideband applications defines by FCC from 3.1GHz to 10.6GHz. Proposed design resonates from (3.21GHz to 12.72GHz) with impedance bandwidth is of 9.51GHz has a moderate gain of 2.88dBi. Parametric analysis is presented to show effect of corner round and ground gap on performance of antenna.Keywords
Corner Rounded, Current Distribution, Ground Gap, UWB, Wideband.
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- Ultra-Low Power Voltage Reference Circuit Utilizing a Threshold Voltage Difference Between Two CNFETs
Abstract Views :155 |
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Authors
Affiliations
1 Department of Electronics and Telecommunication Engineering, Matoshri College of Engineering and Research Center, IN
2 Department of Electronics and Telecommunication Engineering, Vishwabharati Academy College of Engineering, IN
1 Department of Electronics and Telecommunication Engineering, Matoshri College of Engineering and Research Center, IN
2 Department of Electronics and Telecommunication Engineering, Vishwabharati Academy College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 4, No 1 (2018), Pagination: 531-536Abstract
This paper proposes a voltage reference circuit that exploits sub-threshold conduction and threshold voltage difference between two carbon nanotube field effect transistors (CNFETs) to achieve ultra-low power consumption. The circuit produces a reference voltage of 203mV at 0.5V supply voltage, consumes only 3.42pW power and exhibits excellent temperature and power supply independence. The robustness of the proposed circuit for variations in carbon nanotube (CNT) diameter and inter CNT pitch variations is also presented with Monte Carlo simulations.Keywords
Carbon Nanotube Field Effect Transistor, Ultra-Low Power Circuits, Voltage References.References
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